{"id":296,"date":"2024-03-23T02:59:32","date_gmt":"2024-03-22T17:59:32","guid":{"rendered":"https:\/\/www.aisoit.com\/?p=296"},"modified":"2024-03-23T12:57:31","modified_gmt":"2024-03-23T03:57:31","slug":"cpu-isa","status":"publish","type":"post","link":"https:\/\/www.aisoit.com\/?p=296","title":{"rendered":"CPU ISA"},"content":{"rendered":"\n
\"\"<\/figure>\n\n\n\n
ISA Type<\/td>ISA Name<\/td>Maker<\/td>First CPU<\/td><\/tr>
CISC<\/td>IBM System\/360<\/td>IBM<\/td>1964<\/td><\/tr>
CISC<\/td>Intel 8080<\/td>Intel<\/td>1974<\/td><\/tr>
CISC<\/td>MOS 6502<\/td>MOS Technology<\/td>1975<\/td><\/tr>
CISC<\/td>X86<\/td>Intel, AMD<\/td>1979<\/td><\/tr>
CISC<\/td>m68k<\/td>Motorola<\/td>1979<\/td><\/tr>
RISC<\/td>Stanford MIPS<\/td>Stanford University<\/td>1981<\/td><\/tr>
RISC<\/td>ARM<\/td>Arm Holdings, Apple, Qualcomm, Samsung, Renesas<\/td>1985<\/td><\/tr>
RISC<\/td>MIPS<\/td>MIPS Computer Systems, Inc, Loongson, Broadcom<\/td>1986<\/td><\/tr>
RISC<\/td>PowerPC<\/td>Apple\u2013IBM\u2013Motorola alliance, known as AIM, IBM<\/td>1992<\/td><\/tr>
RISC<\/td>Atmel AVR<\/td>Atmel Corporation<\/td>1996<\/td><\/tr>
RISC<\/td>RISC-V<\/td>RISC-V Foundation, StarFive, GigaDevice, T-Head<\/td>2011<\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n

ISA: Instruction Set Architecture<\/p>\n\n\n\n

CISC: Complex instruction set computer<\/p>\n\n\n\n

RISC: Reduced instruction set computer<\/p>\n\n\n\n

MIPS: Microprocessor without Interlocked Pipeline Stages<\/p>\n\n\n\n

ref: https:\/\/cloud.tencent.com\/developer\/article\/1862717?areaId=106001<\/a><\/p>\n\n\n\n

ref: https:\/\/en.wikipedia.org\/wiki\/IBM_System\/360<\/a><\/p>\n\n\n\n

ref: https:\/\/en.wikipedia.org\/wiki\/Intel_8080<\/a><\/p>\n\n\n\n

ref: https:\/\/en.wikipedia.org\/wiki\/MOS_Technology_6502<\/a><\/p>\n\n\n\n

ref: https:\/\/en.wikipedia.org\/wiki\/X86<\/a><\/p>\n\n\n\n

ref: https:\/\/en.wikipedia.org\/wiki\/MIPS_Technologies<\/a><\/p>\n\n\n\n

ref: https:\/\/en.wikipedia.org\/wiki\/PowerPC<\/a><\/p>\n\n\n\n

ref: https:\/\/en.wikipedia.org\/wiki\/List_of_ARM_processors<\/a><\/p>\n\n\n\n

ref: https:\/\/en.wikipedia.org\/wiki\/AVR_microcontrollers<\/a><\/p>\n\n\n\n

ref: https:\/\/en.wikipedia.org\/wiki\/RISC-V<\/a><\/p>\n\n\n\n

RISC Principles<\/h2>\n\n\n\n

The RISC philosophy is specifically targetted at high performance. Its fundamental principle is:<\/p>\n\n\n\n